1. Field of the Invention
The present invention relates to power semiconductor devices having a MOS-gate-metal-oxide semiconductor gate-structure, especially to an insulated gate bipolar transistor used in devices such as invertors that transform or control electric power.
2. Description of the Related Art
In recent years, insulated gate bipolar transistors (hereinafter referred as IGBTs) are utilized, in many cases, as power semiconductor devices including invertors that transform or control electric power. Also, IGBTs are required to obtain larger current capacity (higher withstand voltage) and higher reliability.
FIG. 7 is a plane view of an IGBT-chip that is illustrated in Patent Document 1, for example. In the IGBT-chip 50 illustrated in FIG. 7, a numeral ‘51’ represents an emitter electrode (a first main electrode); ‘52’, a gate pad formed at a concave portion that is provided on a peripheral portion of the emitter electrode 51; ‘53’, gate wiring that extends from the gate pad 52 and is provided on peripheral surface of the emitter electrode 51 and on the inner surface; thereof so as to divide the emitter electrode 51 into strips. IGBT cells 54 having a cellular structure are formed in spaces divided by the gate wire 53.
For example, FIG. 8 is a partially sectional view along Line A-A of one of the IGBT cells 54 in FIG. 7, and shows a cellar structure of a general planar-gate-type IGBT illustrated in Non-Patent Document 1. In FIG. 8, a numeral ‘55’ represents a p+ collector layer (a first semiconductor layer of a first conductivity type) made of a semiconductor substrate; ‘56’, an n+ buffer layer (a second semiconductor layer of a second conductivity type) provided on the top side of the p+ collector layer 55; ‘57’, an n− layer (a third semiconductor layer of the second conductivity type) provided on the n+ buffer layer 56; ‘58’, a p base region (a first semiconductor region of the first conductivity type) provided selectively in the top side of the n− layer 57; ‘59’, an n+ emitter region (a second semiconductor region of the second conductivity type) provided selectively in the top side of the p base region 58; ‘60’, a gate insulation film that is made of a dielectric material such as an oxide film and is provided on the n− layer 57, partially on the n+ emitter region 59 and on the p base region 58 therebetween; ‘61’, a gate electrode that is provided on the gate insulation film 60 and made of a conductive material such as a polysilicon film; ‘62’, an interlayer insulation film that covers the gate electrode 61, the gate insulation film 60 and a portion of the n+ emitter region 59, and is made of a dielectric material such as a silicate glass (hereinafter, referred as a BPSG); ‘51’, an emitter electrode, shown in FIG. 7, that is made of a conductive material such as aluminum and is provided so as to cover on the interlayer insulation film 62, the p base region 58 and a portion of the n+ emitter region 59. A numeral ‘63’ represents a collector electrode (a second main electrode) that is provided on the bottom surface of the p+ collector layer 55 and is made of a conductive material such as aluminum. In addition, the gate electrode 61 is connected to the gate wiring 53 at the electrode ends provided in its extension orientation (in the front-back orientation with respect to the document face in FIG. 8).
Moreover, FIG. 9 is a partially sectional view along Line A-A of the one of IGBT cells 54 in FIG. 7; the figure shows a cellular structure of a planar-gate-type IGBT that has a terrace gate structure shown in Patent Document 2. A terrace gate portion 65 is provided on the n− layer 57 in FIG. 9, which differs from FIG. 8; whose feature is that the IGBT has a thicker gate insulation film 60 than that of the average planar-gate-type IGBT. Herewith, the capacity of the gate insulation film becomes smaller, reducing its feedback capacity. In addition, in FIG. 9, the portions that are identical or equivalent to those in FIG. 8 are represented by the same numerals as those in FIG. 8 so as to omit their explanations.
FIG. 10A and FIG. 10B are a plane view and a partially sectional view along Line A-A of one of the IGBT cells 54 in FIG. 7, respectively; the views illustrate a cellular structure of a trench-gate-type IGBT including a trench that does not work as gate (hereinafter, referred as a dummy trench); the views illustrate, for example, the equivalent IGBT described in Patent Document 2. FIG. 10A shows the IGBT structure, in which the emitter electrode 51 is removed for easy understanding. In FIG. 10, the p+ collector layer 55, the n+ buffer layer 56, the n− layer 57, the emitter electrode 51 and the collector electrode 63 are the portions that are identical or equivalent to those shown in FIG. 8, so that they will be represented by the same numerals as those in FIG. 8 so as to omit their explanations. A numeral ‘66’ represents a p base layer (a fourth semiconductor layer of the first conductivity type) provided on the n− layer 57; a numeral ‘67’ represents a trench gate that extends from the top of the p base layer 66 and reaches the n− layer 57; the trench gate 67 includes a trench 67a, a gate insulation film 67b that lines the trench 67a and is made of a dielectric material such as an oxide film, and a gate electrode 67c that is provided to fill the trench 67a being lined with the gate insulation film 67b and is made of a conductive material such as polysilicon. A numeral ‘68’ represents a dummy trench that extends from the top of the p base layer 66 and reaches the n− layer 57; the dummy trench 68 includes a trench 68a, a gate insulation film 68b that lines the trench 68a and is made of a dielectric material such as an oxide film, and a dummy electrode 68c that is provided to fill the trench 68a being lined with the gate insulation film 68b and is made of a conductive material such as polysilicon so as to be electrically connected to the emitter electrode 51. A numeral ‘69’ represents an n+ emitter region provided in the top of the p base layer 66, contiguously bordering on both sides of the trench gate 67; a numeral ‘70’, an interlayer insulation film that covers a portion of the n+ emitter region 69 and the trench gate 67; the numeral ‘51’, the emitter electrode shown in FIG. 7 that covers uncovered portions of the interlayer insulation film 70, the p base layer 66, the dummy trench 68 and the n+ emitter region 69. With the dummy trenches being provided, current flowing into the IGBT chip 50 due to short circuits can be curbed, which enables the device to secure a short circuit safe operation area (hereinafter, referred as SCSOA) and is effective for increasing current capacity of the device. Here, the end of the gate electrode 67c is connected to the gate wiring 53.
Patent Documentation 1
Japanese Patent Laid-Open No. 1996-316479 (FIG. 1)
Patent Documentation 2
Japanese Patent Laid-Open No. 2002-353456 (FIG. 1)
Non-Patent Documentation 1
“Transistor Technology Special,” No. 85 Jan. 1, 2004, page 44 (FIG. 3 through FIG. 10), CQ Publishing Co. Ltd., Tokyo, Japan
Non-Patent Documentation 2
“Power Semiconductor Device and Power IC Handbook,” 1996, page 151 (FIG. 6.28a), Corona Publishing Co., Ltd.
An IGBT that is a conventional power semiconductor device has been configured as described above; recently, it is required that IGBTs obtain larger current capacity (higher withstand voltage) and higher reliability; the following problems have now drawn attention in order to meet those requirements.
In the IGBT chip 50, in order to reduce each gate resistance (represented as ‘R’ in FIG. 7) of the gate electrodes 61 and 67c formed of a conductive material such as polysilicon, the gate wiring 53 formed of a conductive material such as aluminum is provided as shown in FIG. 7, so as to divide the emitter electrode 51 into strips. In order to cope with larger current capacity and higher reliability, the number of wires that are made of a conductive material such as aluminum and bonded to the emitter electrode 51 tends to increase in an IGBT package where the IGBT chip 50 is mounted. Therefore, in order to enhance the reliability of the wire-bonding, it is necessary to enlarge areas for each strip of the emitter electrode 51 by giving more spaces between the gate wiring 53; however, enlarging the areas meanwhile causes big difference between the gate resistances of the gate electrodes 61 and 67c, as have been described above. More specifically, in the IGBT cells 54, when a cell is located near to the gate wiring 53, the gate resistance thereof becomes small; when it is located apart from the gate wiring 53 (for example, located at the intermediary point between the gate wiring), the gate resistance thereof becomes large. Therefore, when the IGBT chip turns off, a current supplied to one of the IGBT cells 54 close to the gate wiring 53 and a current supplied to another one of the IGBT cells 54 apart from the gate wiring are not balanced (hereinafter, referred as imbalance among current diversions); then, currents are concentrated on such IGBT cells 54 that are located apart from the gate wiring 53 and whose turning off speed becomes slow, so that the IGBT cells generate heat; therefore, turn-off withstand ability, that is, a reverse-biased safe operating area (hereinafter, referred as RBSOA), becomes reduced.
As a means for reducing the gate resistance of the gate electrodes 61 and 67c, it is considered to use doped polysilicon that is a polysilicon—the material of the gate electrodes 61 and 67c—doped with impurities in order to reduce their resistance. However, when doped silicon is used for the gate electrode 61 of the planar-gate-type IGBT shown in FIG. 8 and FIG. 9, auto-doping of impurities, with which a polysilicon has been doped, into the gate insulation film 60 and the n− layer 57 occurs, adversely affecting the gate-emitter leakage current and the primary-voltage-to-leakage-current characteristics. Also, when doped silicon is used for the gate electrode 67c of the trench-gate-type IGBT shown in FIG. 10, because the width of the trench gate is formed very narrow, the cross-sectional area of the gate electrode 67c becomes small. Therefore, in the above-described case where the spaces between the gate wiring 53 become wider, the gate resistances increase, causing the imbalance among current diversions to occur, so that its turn-off withstand ability will be reduced.